This application is related to U.S. Pat. application Ser. No. 170,399, now U.S. Pat. No 5,008,812, entitled "Context Switching Method and Apparatus for Use in a Vector Processing System," by D. Bhandarkar et al.; U.S. Pat. application Ser. No. 170,393, now U.S. Pat. No. 5,043,862, entitled "Exception Reporting Mechanism for a Vector Processor," by D. Bhandarkar et al.; and U.S. Pat. application Ser. No. 170,395, now U.S. Pat. No. 4,945,250, entitled "Method an Apparatus for Executing Instructions for a Vector Processing System," by D. Bhandarkar et al., which are herein incorporated by reference.
The invention relates generally to data processing systems which are capable of executing vector instructions, and specifically to such systems which need to react to memory management exceptions.
Certain high performance data processing systems include, in addition to a main or scalar processor, a separate vector processor to process vector instructions quickly and efficiently. Vector instructions direct a processor to perform memory, arithmetic or logical operations on data represented as vectors. The main or scalar processor processes the other type of instructions, called "scalar" instructions. Scalar instructions, for example, direct a processor to perform memory, arithmetic, or logical operations on logical or scalar data.
When an instruction executing in a vector processor attempts to access a page of memory which is not currently resident, or when that instruction attempts to access a protected portion of memory, a memory management fault or "exception" results which triggers an operating system routine. In data processing systems containing both vector processors and scalar processors, the technique chosen to handle a memory management exception from the vector processor can have significant ramifications. For example, in many systems the vector processor will interrupt the scalar processor, which reduces the efficiency of the scalar processor. In other systems, the possibility of a memory management exception will prevent the vector and scalar processors from operating independently.
The problems of memory management handling are compounded is a data processing system which is sequentially executing portions of several processes, or in other words, providing context switching. If the vector processor and scalar processor are truly operating independently, the scalar processor may already be executing instructions on the next process while the vector processor is still executing instructions from a previous process. If a memory management exception occurs during the vector processor execution and causes an interrupt, the process in the scalar processor would be interrupted even though it is different from the process in the vector processor for which the exception occurred.
One solution to this latter problem would be to prevent the scalar processor from operating on the next process until the vector processor finishes the process. This solution, however, greatly diminishes the efficiency of the data processing system.
Additional problems with memory management exceptions occur when "chaining" or overlapped processing occurs. A vector processor which has chaining capability may be executing a vector memory instruction, such as a load or store instruction, and executing a vector add instruction which relies on data from the vector memory instruction. If a memory management exception occurs during execution of the memory instruction, the technique for managing that exception must ensure that the faulting instruction can be restarted with no loss of data. The easy solution is to prevent such chaining.
For high performance, vector operations should be executed independently of scalar operations. If this includes access to vector data in virtual memory, a method must exist for reporting, handling, and recovering from memory management exceptions. These are part of normal operation, and must not interfere with a user program. When the scalar processor and the vector processor perform the vector memory operations together, the exceptions are said to be handled synchronously, and the method used for scalar memory exceptions apply. When the vector processor does the memory operations independently, the exceptions are said to be asynchronous.
It would be beneficial, however, to employ a new method for reporting these exceptions to the operating system, correcting the condition, and restarting the vector processor without loss of data. The benefit of doing this, is that not only can memory references be executed faster, but subsequent arithmetic operations in the vector unit can be overlapped.
In addition, it would also be beneficial if chained vector instructions being executed by the vector processor when an exception occurs and which do not use data from the faulting instruction, could complete execution despite the occurrence of a memory management exception due to the faulting instruction. cl SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to minimize the system overhead required to report memory management exceptions asynchronously and reissue vector memory operations after the exception has been handled by operating system software.
Another object of the invention is to provide memory management handling for a vector processing unit which does not interrupt the scalar processing unit.
Yet another object of the invention is to provide a technique for minimizing the operations to be repeated when a memory management exception occurs during chained operations in a vector processor.
Another object of the invention is to allow resumption of vector instructions which are already partially complete and cannot be restarted from the beginning.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, a data processing system of this invention contains a memory and is capable of processing vector instructions and scalar instructions, the vector instructions involving data processing operations on vector quantities and accesses to the memory, and the scalar instructions involving data processing operations on non-vector quantities. The vector instructions are executed by performing a plurality of suboperations.
The data processing system of this invention comprises scalar processing means for executing scalar instructions, vector processing means for executing vector instructions simultaneously with the execution of the scalar instructions by the scalar processing means, and exception record means for recording into a state means, as part of the vector state information, an indication of the occurrence of the memory management exception and sufficient information about the vector processing means such that the vector processing means can later resume execution at the one of said suboperations of the faulting vector processing instruction during which the memory management exception occurred.
The vector processing means includes state means for holding vector state information representing an execution state of the vector processing means, exception detecting means for indicating the presence of a memory management exception occuring during one of said suboperations of a faulting one of said vector processing instructions, and vector operation halting means, coupled to said exception detecting means, for halting said vector processing means without interrupting the execution of said scalar instructions by said scalar instruction processing means, when said execution detecting means indicates the presence of said memory management exception.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention.